Testing and debugging of a new application specific integrated circuit (ASIC) or of a new or modified application program running on an ASIC requires insight into the internal workings of busses and program execution. The IEEE 1149.1 (JTAG) standard has proven to be a very robust solution to a variety of test and debug systems, enabling a rich ecosystem of compliant products to evolve across virtually the entire electronics industry. Yet increasing chip integration and rising focus on power management has created new challenges that were not considered when the standard was originally developed. The Mobile Industry Processor Interface (MIPI) Test and Debug Working group has selected a new test and debug interface, called P1149.7, which builds upon the IEEE1149.1 standard. P1149.7 enables critical advancements in test and debug functionality while maintaining compatibility with IEEE 1149.1. In addition to P1149.7, the MIPI test and debug interface specifies how multiple on-chip test access port (TAP) controllers can be chained in a true IEEE1149.1 compliant way. It also specifies a System Trace Module (STM). STM consists of a System Trace Protocol (STP) and the Parallel Trace Interface (PTI). The signals and pins required for these interfaces are given through the ‘MIPI Alliance Recommendation for Test & Debug—Debug Connector’, also part of the MIPI test and debug interface. The main blocks of the MIPI Debug and Trace Interface (DTI), seen from outside of the system, include: a debug connector; the basic debug access mechanism: JTAG and/or P1149.7; a mechanism to select different TAP controllers in a system (Multiple TAP control); and a System Trace Module.
The System Trace Module helps in software debugging by collecting software debug and trace data from internal ASIC buses, encapsulating the data, and sending it out to an external trace device using a minimum number of pins. STM supports the following features:                Highly optimized for SW generated traces        Automatic time stamping of messages        Allows simultaneous tracing of 255 threads without interrupt disabling        Configurable export width 1/2/4 pin+dedicated clock+optional return channel                    Minimal pin usage 2 pin (1 data+1 clock)            Maximum pin usage 6 pins (4 data+1 clock+1 return channel)                        Maximum planned operating frequencies 166 MHz (double data rate clocking)        Provides a maximum bandwidth of slightly above 1 Gbit/s (theoretical max. 1.6 Gbit/s)        Supports up to 255 HW trace sources        Support for 8, 16, 32 and 64 bit data types        
A maximum of 255 different bus masters can be connected to the STM trace port via a bus arbiter. The bus masters can be configured for either SW or HW type to optimize the system for different types of trace data. SW type master messages are used to transmit trace data from OS processes/tasks on 256 different channels. The different channels can be used to logically group different types of data so that it is easy to filter out the data irrelevant to the ongoing debugging task. The message structures in STM are highly optimized to provide an efficient transport especially for SW type master data.